Transistorized inverters



8- 26, 1 R. M. HUBBARD 2,849,673

'TRANSISTORIZED INVERTERS Filed Oct. 8. 19 56 ,20 /,2 LOCATION OUTPU T 4 r0 N OUTZPUT 4 LOAD INVEN TOR. R BERT M. HUBBARD hysteresis loop cores sired to the end changing load conditions cuit arrangement will appear as 2,849,673 TRAN SISTURTZED INVERTERS Application October 8, 1956, Serial No. 614,397 8 Claims. (Cl. 321-44) This invention relates to improvements in inverters of a type using transistors and transformers with. square for converting direct voltage into square-wave alternating voltage. A general object thereof is to provide an inverter of that type adapted for the regulation or adjustment of inverter frequency independently of output voltage or load. The invention isherein illustratively described by reference to its presently preferred form; however, it will be recognized that certain modifications and changes therein w'th respect to details may be made without departing from the essential features involved.

The use of junction transistors as controlled switches in conjunction with square hysteresis loop core transformers for producing square-wave alternating voltage in a multi-vibrator type circuit arrangement has been proposed heretofore. In the former circuit, the various timing and output windings were comprised in a single transformer, and since operating frequency depends on the magnitude of applied direct voltage, any attempt to regulate applied voltage and thereby operating frequency required that the regulator have the capacity to handle output power as well as frequency control power. quired a complex regulator of relatively large capacity. Moreover, the interdependence of frequency control voltage and output voltage resulting from the use of a common transformer core for the timing and output windings precluded the independent adjustment or regulation of operating frequency and output voltage. Also the transformer core design was necessarily based on a compromise between the inconsistent requirements for optimum timing control characteristics and optimum power transfer charactistics of the transformer.

In general the present invention provides a. transistorized inverter which overcomes the above mentioned limitations of the former circuit while retaining the important advantages thereof. This is brief it accomplishes by the complete separation of the timing control function from the power delivery function of the circuit, using separate transformers for the performance of these two functions. Thus, the power delivery or output transformer may be made of optimum power transformer design, whereasthe timing control transformer may be made of optimum design for its purpose using the principle of a square hysteresis loop core for controlling the switching action of the transistors. Separate direct voltage sources for the timing and power delivery functions may be used if dethat independent regulation and/or adjustment of inverter frequency andoutput voltage may be achieved. Also, improved frequency stability under is realized because of the independence of. the load and timing portions of the circuit. These and other features and advantages of the novel cirthe description proceeds on the basis of the accompanying drawings.

Figure 1 is a schematic diagram of the timing portion of the improved circuit.

That rerent cutoff. During the progressive 2,849,673 Patented Aug. 26, 1958 Figure 2 is a somewhat idealized graph of the timing transformer core characteristic showing what is meant by a square hysteresis loop. I

Figure 3 is a schematic diagram of the complete circuit in its presently preferred form.

Figure 4 is a schematic diagram of a modified circuit arrangement using a single direct voltage source while retaining separation of the timing and power delivery portions of the circuit.

Referring to Figures 1 and 2, the timing portion of the circuit shown in the former figure comprises a source 10 of direct voltage E having the polarity indicated, junction transistors 12 and 14 having emitter, collector and base electrodes, and transformer 16 having a square hysteresis loop core, a pair of similar secondaries (N of N turns each, and a pair of similar primaries (N of N turns each. The secondaries N are respectively series connected with the emitter-base electrodes of the respective transistors, with the transistor emitters being connected to the positive terminal of source 10 and to the mutually adjacent but oppositely poled ends of secondaries N The primaries N are respectively series connected with the respective transistor collectors, and

their remaining, mutually adjacent but oppositely poled ends are connected to the negative terminal of source 10.

When voltage E is applied, one transistor will conduct more emitter-collector current than the other due to inevitable slight differences in electrical characteristics of the transistors. The difference between the resulting currents flowing in the respective windings N will therefore produce a flux change in the core of transformer 16. The establishment of this flux change will induce feedback voltages in the secondary windings N which will be applied as base drive voltages to the transistors. The feedback voltages are of such a polarity as to increase the collector current in the more conductive transistor while decreasing the collector current in the less condutive transistor. This produces a further difference in current flow in the primary windings N and a further increase' in core flux change. The net result is that one transistor is progressively driven to collector current saturation while the other isdriven at the same rate to collectorcurchange, the core flux the directhe knee or break in the square of the transformer will continue to increase in tion indicated until I hysteresis loop of the core is reached (Figure 2). At that instant, when core flux density has arrived at the point of substantial saturation of the core, the feedback voltage is greatly reduced because the rate of change of flux has suddenly dropped. As a result, the transistor base drive becomes insufficient to maintain the conductive transistor in its high level of saturation, and some reduction in conductivity thereof takes place. The resulting reduction of -.core flux in the' transformer causes a reversal in polarity of the induced voltages in secondariesN With reversed base drive, the saturated transistor is driven progressively towards cutoff and the cutoff transistor towards saturation. The flux density in the transformer core A is now progressively changed from one saturation level toward the opposite level, following the hysteresis loop indicated in Figure 2. When the opposite level of saturation is reached the cycle repeats itself.

It may be shown that the switching frequency in such a circuit is substantially:

4AN B where A is the core cross-section of the transformer and B is the flux density per unit of cross-sectional area of the core at the effective value of core saturation. It is therefore evident that frequency of operation of the circuit is proportional to applied timing voltage *voltage E from the direct voltage source 18 to the respective oppositely poled primaries N of power transformer 20 in alternate sequence.

transformer secondary N may be arranged to be connected to any suitable load (not shown). In the arrangevment of Figure 3, separate direct voltage sources and 18 are used for the timing portion of the circuit and In this used, independent adjustment of frequency may be effected by varying the timing voltage E without affecting at all may be provided separately in the source 18.

of the primaries. This insures independence of the timing and power transfer functions. In the illustrated positions of the diodes d they are effective to accomplish this result if the sum of B and the voltage induced in a power transformer primary N is less than the sum of E and the voltage induced in the associated timing transformer pri- If the reverse is true, these diodes must he placed in their alternative locations in the direct leads for the timing control transformer primaries N as indicated in the figure. The need to consider alternative positions for the decoupling diodes arises from the use of separate direct voltage sources 10 and 18 for the two portions of the circuit.

In the modification shown in Figure 4 a single direct voltage source 20 serves both the timing portion and the power transfer portion of the circuit. coupling diodes are located at the places indicated, namely in the direct leads for the power output transformer primaries N While the simplified It Will of course be evident that the shape of the outby the connection of suitable filtering or wave-shaping networks to the power transformer secondary N al- 4 though the circuit as shown is essentially a square-wave generator. f

The circuit is readily designed to achieve stability of operation due to the fact that the transistors as switches are the only elements common to both the timing circuit zero to full load with less than 1% change of frequency.

Also the output voltage regulation is dependent on the closed-circuit impedance of the transistor as a switch. With the same set of conditions as those mentioned in the preceding paragraph it was found readily possible to permit the load to vary throughout its full range with less than 1% change of output voltage.

Another practical design consideration resides in the selection of the core material for the timing control transformer 16. This core material may be Hypernik-V. The nickel-iron materials, such as Hymn are also Still others may also be used.

N If the exciting current is small compared to the full load current and the regulation is reasonably good (i. e., relatively low IR drop due to exciting and switching currents flowing in the windings N the squareness of the when voltage timing portion of the circuit.

These and other aspects of the invention will become evident to those skilled in the art.

I claim as my invention:

1. A circuit for converting direct voltage into alternating voltage, comprising two transistors each having emitto the oppositely poled end of the other primary, means connecting the remaining ends of said primaries to the transistor collectors, respectively, thereby to form a selfthe collector and emitter of the other transistor in series with the other such output transformer primary to pass direct current through the latter with a polarity opposite to that of the first such primary during periods of transistor conductivity between such latter collector and emitter, thereby to induce alternating voltage in such output transformer secondary during self-oscillation of said self-oscillating circuit.

2. The circuit defined in claim 1, wherein all of the named sources of direct voltage comprise a single source of direct voltage.

3. The circuit defined in claim 2, and unidirectionally conductive elements respectively interposed directly in series with each of the respective output transformer primaries with a polarity permitting said flow of direct current therethrough while blocking reverse flow of direct current therethrough, thereby to isolate the windings of the timing control transformer from induced voltages in the primaries of the power output transformer.

4. ,The circuit defined in claim 1, wherein the last two mentioned sources of direct voltage comprise a single source of direct voltage separate from the first mentioned source of direct voltage.

5. The circuit defined in claim 4, wherein the two separate voltage sources in series with one of the timing control transformer primaries and the corresponding power output transformer primary form one potential interaction circuit, and the two separate voltage sources in series with the other such primaries form a second potential interaction circuit, and unidirectionally conductive means interposed in each such potential interaction circuit at a location therein preventing induced voltage in either such power output transformer primary from passing current through the associated timing control transformer primary while permitting normal flow of current through such power output transformer and timing control transformer primaries attending operation of the circuit.

6. A transistorized inverter comprising two transistors each having emitter, base and collector electrodes, one pair of such electrodes comprising control electrodes and a second pair of such electrodes comprising load electrodes, a first direct voltage source, a timing transformer having a pair of primaries, a pair of secondaries and a core common thereto of the type presenting a square" hysteresis loop, means connecting each of said primaries in series with said source and the load electrodes of one of the respective transistors to pass current through said primaries with relatively opposite polarity during conductivity of the respective transistors between their load electrodes, means connecting the control electrodes of each transistor in series with one of the respective sec- 1 necting said second direct voltage source in series with the load electrodes of the other transistor and the other of said power output transformer primaries, with relatively opposite polarity of said power output transformer primaries, thereby to induce alternating current in said power output transformer secondary accompanying selfoscillation of said self-oscillation circuit, and unidirectionally conductive means in circuit with said timing and power output transformer primaries preventing induced voltages in said power output transformer primaries from passing current through said timing transformer primaries without preventing normal current flow through any of said primaries.

7. The combination defined in claim 6, wherein one of the direct voltage sources is varia le independently of the other.

8. The combination defined in claim 6, wherein the first and second direct voltage sources comprise a single source.

References Cited in the file of this patent UNITED STATES PATENTS 2,748,274 Pearlman May 29, 1956 2,757,243 Thomas July 31, 1956 2,791,739 Light May 7, 1957 

